EPROMS are memories well known to those skilled in the art. Each cell includes at least one floating-gate transistor and one access transistor. According to the usual matrix architecture of memories, each cell is controlled by a bit line and a word line of the memory. Each cell can thus be read or written individually by the selection of the corresponding bit line and word line.
It is also common practice to provide for a word access to the memory. Many data elements in applications are encoded not on one bit alone, but on several bits. The common memory architectures thus provide for the possibility of simultaneously accessing several bits, typically 8, 16 or 32 bits. In all cases, the basic unit in terms of a memory word is the byte, formed by eight bits. Most memory architectures are based on the byte.
In practice, the eight bits of a byte are located on the same word line. In the case of a 16-bit memory, the memory array is generally divided into two. A 16-bit word is formed by one byte in one half-array and by another byte in the other half-array. Because of the large memory capacities that are being sought, a word line provides access to several bytes. For example, it is possible to have 128 bit lines for 128 word lines. Each word line thus contains 16 bytes.
To simultaneously select all the bits of a word of a word line, there is a provision for grouping the words of the memory into columns. The i ranking column is the one that comprises the word of the same rank in each word line. An architecture of this kind calls for additional access transistors, each making it possible to select a particular column of the memory. Depending on the specifications of the memory access operations, there are various architectures available to the designer.
One example of a memory architecture organized in word columns of n memory cells is shown in FIG. 1. This architecture provides one additional access transistor per word of the memory. If the memory has p word lines and N columns, there are p access transistors per column, i.e., one per word line, this gives a total of pxN additional access transistors, i.e., one per word. These additional access transistors receive a signal for the selection of the associated word line as well as a signal for the selection of the associated column. These signals are given by the address decoding circuit of the memory.
FIG. 1 shows a memory organized in word columns of n=8, memory cells C.sub.0 to C.sub.7 comprising p word lines W1.sub.0 to W1.sub.p-1, and N columns Col.sub.0 to Col.sub.N-1. Each column has eight bit lines B0 to B7, each connected to the same ranking cells of the words of the column.
Each memory cell has an access transistor Ta series-connected with a floating-gate transistor Tf. The access transistor Ta is connected at its gate to the corresponding word line and at its drain to the corresponding bit line. An additional column access transistor is planned per word. This column access transistor, for example, Tc.sub.0,0, is connected at its gate to the corresponding word line W1.sub.0 and at its drain to the corresponding column selection line Col.sub.0. At its source, it transmits a word selection line Sel.sub.0,0, applied to the control gate of the floating-gate transistors of the cells C.sub.0 to C.sub.7 of the word considered.
Typical EEPROM memory architectures comprise source lines to draw the sources of the memory cells to ground, especially for reading. In the case of a word access memory architecture, one line source per column is provided. The source line LS.sub.0 for the column Col.sub.0 connects the sources of the floating-gate transistor of the memory cells of this column to a corresponding ground connection transistor MS.sub.0.
Referring again to FIG. 1, there are N source lines LS.sub.0 to LS.sub.N-1 and N ground connection transistors MS.sub.0 to MS.sub.N-1, i.e., one per column. The number of these transistors depends typically on the memory architecture chosen by the designer, application constraints, and the design and drawing rules. It is thus possible to have a single ground connection transistor for the entire memory array, provided that it can let through all the current needed into the different access modes of the memory.
A problem that arises with the word access memory architectures is in the connection of the sources of the floating-gate transistors of the memory cells to a ground connection transistor that is outside the memory array. The sources of the memory cells are diffusions. The connection of these diffusions to a ground connection transistor must take account of the layout constraints related to the technology, and must use as little layout space as possible.
The aim is to obtain a small-sized and low cost finished product. One metal source line per column is typically used to connect the diffusion of the sources of the memory cells to the ground connection transistor. This source line must be located outside the layout zones of the memory cells so as not to add an additional metal layer level in the integrated circuit.
FIG. 2a shows the partial layout of the first two words of two consecutive word lines WL.sub.1 and WL.sub.2. This layout shows the making of one diffusion zone for each word. In the first column Col.sub.0 of the memory, the diffusion zone LD.sub.1,0 forms the source s.sub.0, . . . , S.sub.7 of each of the floating-gate transistors of the memory cells C.sub.0 to C.sub.7 of the first word of the word line W1.sub.1. The diffusion zone LD.sub.2,0 forms the source s.sub.0, . . . , s.sub.7 of each of the floating-gate transistors of the memory cells C.sub.0 to C.sub.7 of the first word of the word line W1.sub.2.
In the second column Col.sub.1 of the memory, the diffusion zone LD.sub.1,1 forms the source s.sub.0, . . . , s.sub.7 of each of the floating-gate transistors of the memory cells C.sub.0 to C.sub.7 of the second word of the word line Wl.sub.1. The diffusion zone LD.sub.2,1 forms the source s.sub.0, . . . , S.sub.7 of each of the floating-gate transistors of the memory cells C.sub.0 to C.sub.7 of the second word of the word line W1.sub.2.
Each of these diffusion zones thus forms a diffusion line in a direction perpendicular to the sources. Each diffusion line is formed to a respective contact used to connect it to a metal source line of the associated, perpendicular column. The contact and the source line are made outside the layout zone of the memory cells of the column considered. In the example, for diffusion lines LD.sub.1,0 and LD.sub.2,0, there correspond respectively the contacts P1, P2 on the metal source line LS.sub.0 of the column Col.sub.0. To the diffusion line LD.sub.1,1 and LD.sub.2,1, there respectively correspond the contacts P3, P4 on the metal source line LS.sub.1 of the column Col.sub.1.
According to this layout, two successive columns are separated from each other by a metal source line. With a layout of this kind, there is a loss of current in the connection path of the sources at the ground connection transistor. The diffusion zones are resistive, and induce a considerable loss of current as a function of length. The amount of this loss of current varies for each cell within the same word.
Referring again to FIG. 2a, the cell C.sub.7 of a word is connected to the source line by a smaller diffusion length than is the cell C.sub.0 of the same word. Thus, the loss of current in the cell C.sub.7 is smaller than in the cell C.sub.0. In other words, the loss of current in a cell of a word, due to the diffusion length for connecting the source of this cell of a word to the corresponding source line, is a function of its rank in this word.
This loss of current is very troublesome, especially in the word read access mode. It may be recalled that the EEPROM memory cells, which are blank when they come off the production line, can then be electrically programmed. This lowers the threshold voltage of their floating-gate transistor. Alternatively, the EEPROM memory cells may be electrically erased, thus increasing this threshold voltage.
If the memory cells are read under voltage bias conditions such that a blank cell is conductive, the result thereof is that, in read mode, an erased cell is not conductive and a programmed cell is conductive. The principle of reading memory cells relies on the current/voltage conversion.
A differential amplifier is thus planned for each bit of the word to be read. This differential amplifier receives, at input, the current from the cell selected for reading and a reference current. This reference current is generally given by a reference memory cell that is a blank cell. The read bias conditions are such that the blank reference cell is conductive, and the cell in the programmed state conducts greater current while an erased cell is not conductive.
In a numerical example, the typical current values at 5 volts of the supply voltage will be:
I.sub.p =50 microamps (programmed cell); PA1 I.sub.v =25 microamps (blank cell); and PA1 I.sub.e =0 (erased cell).
Considering the case where the memory cells C.sub.0, . . . , C.sub.7 of a word are all programmed, subjected to the same bias conditions in the read mode, then in theory they should all let through the same current. However, because of the different resistive path in each cell between the source and the ground connection transistor, there is a different current in each cell. The strongest current is in the cell that is geographically the closest to the source line, which is C.sub.7 in the example. The lowest current is in the cell that is furthest away, which is C.sub.0 in the example.
FIG. 2b gives a view, for the first word of the word line W1.sub.1, of the equivalent resistors R0, R1 and R2 of the diffusion zone. Resistor R0 is for the part of the diffusion between the contact P1 and the source of the closest cell, which is C.sub.7. Resistor R1 is for each part of the diffusion forming a source of a memory cell. Resistor R2 is for the diffusion parts between two consecutive sources.
If it is assumed that the cells C.sub.0 to C.sub.7 are in an identical state, i.e., all conductive (blank or programmed), then it is easy to compute the current in each cell. Assuming a=R2/R1 and i0 to be the current flowing through the cell C.sub.0, current values are as follows: EQU i1=i0+a.times.i0 EQU i2=i0+(3a+a.sup.2).times.i0 EQU i3=i0+(6a+5a.sup.2 +a.sup.3).times.i0 EQU i4=i0+(10a+15a.sup.2 +7a.sup.3 +a.sup.4).times.i0 EQU i5=i0+(15a+35a.sup.2 +28a.sup.3 +9a.sup.4 +a.sup.5).times.i0 EQU i6=i0+(21a+70a.sup.2 +84a.sup.3 +45a.sup.4 +11a.sup.5 +a.sup.6).times.i0 EQU i7=i0+(28a+126a.sup.2 +210a.sup.3 +165a.sup.4 +66a.sup.5 +13a.sup.6 +a.sup.7).times.i0
Thus, the maximum current difference is given by: EQU .DELTA.I=i7-i0=(28a+126a.sup.2+210 a.sup.3+165 a.sup.4+66 a.sup.5+13 a.sup.6 +a.sup.7)i0, with a&lt;1.
Since the current in the cells C.sub.0, . . . , C.sub.7 in the same state (programmed for example) are not identical, the time for setting up each of the bits of a word to be read is not the same. This causes deterioration in the memory read access time, and reading may become impossible in an operational mode. Furthermore, at a low supply voltage, these currents are lower. The difference between several standard values also becomes smaller. For example, I.sub.p may decrease from a standard value to 20 microamps, and I.sub.v to 10 microamps. Depending on the position of the bit in the word to be read, the current of a program cell may become too close to the reference current, leading to an erroneous reading.
To overcome this problem of variation of the programming current between the cells of a word to be read due to the resistivity of the diffusion line, it is proposed in the prior art to use a double-word architecture. The basic idea of this approach is to increase the mean value (or standard value) of the programming current. Thus, the variations have a lower effect on the reading in terms of reliability and access time.
The general principle is thus as follows. When a word is selected in the read mode, a second word is automatically selected to recover twice the current of a cell on each bit line. Thus, an increase is obtained in the difference between the programmed state and the erased state as compared with the reference, so that the differential reading is made more reliable. The implementation of this approach is particularly simple for 8-bit memories.
It is a common practice to use the memory array of 16-bit memories in which a half-array is disabled to obtain 8-bit memories. To implement the approach of the prior art, it is enough to enable the second half-array in the read mode by a word and modify the decoder to obtain the automatic selection of a word in a second half-array when the word is accessed in read mode in the first half-array. It must be furthermore planned that the cells of the second half-array will all be in the same state, either erased or programmed or blank.
Considering only the programmed cells, at the level of each bit line, twice the current of a cell is recovered, giving: EQU I(B0)=2i0 EQU I(B1)=2i1=2i0+(2a)i0 EQU I(B2)=2i2=2i0+(6a+2a.sup.2)i0 EQU I(B3)=2i3=2i0+(12a+10a.sup.2 +2a.sup.3)i0 EQU I(B4)=2i4=2i0+(20a+30a.sup.2 +14a.sup.3 +2a.sup.4)i0 EQU I(B5)=2i5=2i0+(30a+70a.sup.2 +56a.sup.3 +18a.sup.4 +2a.sup.5)i0 EQU I(B6)=2i6=2i0+(42a+140a.sup.2 +168a.sup.3 +90a.sup.4 +22a.sup.5 +2a.sup.6)i0 EQU I(B7)=2i7=2i0+(56a+252a.sup.2 +420a.sup.3 +330a.sup.4 +132a.sup.5 +26a.sup.6 +2a.sup.7)i0.
However, the amplitude of the current variation is doubled: I(B7)-I(B0)=56a+252a.sup.2 +420a.sup.3 +330a.sup.4 +132a.sup.5 +26a.sup.6 +2a.sup.7 =2.DELTA.I.
In theory, if the additional word automatically selected in the read mode contains programmed cells, it is possible to obtain the following read currents: I.sub.p =100 microamps under a 5 volt supply, I.sub.p =50 microamps under a 2.5 volt supply, I.sub.v is unchanged, and I.sub.e always equals 0. However, the increase in current is limited by the ground connection transistor, especially at a low supply voltage. The current flowing into the cells is not doubled. This current is increased only slightly, so much so that this approach proves to be inadequate.
All that has been explained with reference to an EEPROM can be applied equally well to a flash EPROM type memory whose architecture comprises blocks of memory cells with a common source line. More generally, it can be applied to a non-volatile memory of the electrically erasable and programmable type.
In the prior art, the mean value of the read current is increased for reading the bits of the word to be read. Thus, the maximum difference between the read currents undergoes little or no change. It is the difference with the reference current that is increased.